1. Field of the Invention
The present invention relates to a device structure of a MOSFET.
2. Description of the Related Art
The market is demanding high-performance and low-cost radio frequency (RF) LSIs. In particular, there have been widely used device structures of MOSFETs provided with excellent RF characteristics by CMOS processes.
As transistor sizes are reduced in order to achieve high transistor densities, the short channel effect due to short gate lengths makes it difficult to control drain currents by gate voltages, and causes a phenomenon called punch-through. To inhibit this phenomenon and improve gate controllability, it is effective to employ a multigate MOSFET having gate electrodes disposed on both top and under sides of a channel portion, and being capable of fully controlling the channel by the gate electrodes. To realize this multigate structure, it is difficult to form a gate electrode on the under side of the channel portion by a conventional planar MOSFET fabrication method. For this reason, multigate field-effect transistors having structures in which gate electrodes are disposed on two opposite sides of a fin-shaped channel portion standing perpendicular to a substrate have been proposed, and the structures have been known as “fin FET” structures (e.g., JP-A 2009-182360 and JP-A 2011-181952).
In one of fin fabrication methods, for example, as disclosed in JP-A 2009-182360, predetermined regions of a semiconductor film made of Si, SiGe, or the like are etched using photoresist (hereinafter also referred to as PR) or the like, and a protruding portion between the etched regions is used as a fin.
Meanwhile, various structures of fines have been proposed, such as an I-shaped fin disclosed in JP-A 2009-182360 and a U-shaped fin disclosed in JP-A 2011-181952.
In the case where a thin film is etched to form a fin, certain roughness exists in side walls of the fin after processing. Use of fins having such roughness in transistors may cause a problem of variations in characteristics among the transistors due to their shapes or the like. As a method of reducing the roughness of side walls of a thin film after etching processing, a method disclosed in JP-A 2006-209128 has been known. In JP-A 2006-209128, before etching of a predetermined thin film, side walls of a patterned mask film provided on the thin film are covered with a carbon film to reduce roughness, and then the thin film is etched.
However, to reduce the roughness of the side walls, a certain amount or more of a carbon film needs to be deposited on the side walls. Accordingly, in the case where this method is applied to fin FETs required to have a high integration density, widths of grooves between patterned masks become so small that problems may occur such as the difficulty of etching a semiconductor film, and reductions in shape accuracy and size accuracy.